1. Field of the Invention
The invention relates to testing of integrated circuits. More specifically, the invention relates to a method and an apparatus for testing integrated circuits having multiple clock domains.
2. Related Art
As the complexity of integrated circuits has increased, chip designers have increasingly become dependent on EDA tools (electronic design automation). Furthermore, EDA tools have allowed addition of more features for testing the integrated circuits. In addition to testing the design of the integrated circuits, most EDA tools also support design for testability (DFT), which allows testing of a manufactured integrated circuit.
The most common design for testability feature is the inclusion of one or more scan chains in an integrated circuit. Scan chains are formed by tying scan elements, such as internal registers, flip-flops, and other storage elements, in series. The scan chains are then tied to external chip pins via bonding pads. The elements in the scan chain have two functional modes. In the “normal mode”, the elements in the scan chain perform the intended logic functions of the integrated circuit. In the “scan mode”, the elements of the scan chain are configured to serially receive data or to serially output the current state of the elements in the scan chain. For example, test vectors can be scanned into the scan chain, then the integrated circuit is allowed to function as intended for one or more clock cycles. Then the data from the scanned chain is read to determine whether the integrated circuit performed correctly. The, two main type of scan chain testing are DC scans and AC scans. Furthermore, additional storage elements can be added to the scan chain to allow control bits to be stored in the integrated circuit during testing.
For DC scans, the test vectors are scanned into the integrated circuit at a slow scanning frequency. Then the chip is operated at a testing frequency (often the same as the scanning frequency) that is typically much lower than the actual operating frequency of the integrated circuit. Thus, DC Scans are well suited for finding “stuck bits” and other low frequency issues. However, DC Scans are not suited for finding race conditions, delay issues, and other problems that only occur at high frequencies. AC scans are designed to catches these high frequency issues.
In AC scanning the test vector is loaded at the scanning frequency, then testing occurs at or near the operating frequency. While, AC scanning can be done using clock signals from the test equipment coupled to the integrated circuit, more accurate results are obtained by using clock signals generated by a phase locked loop within the integrated circuit. The two most common AC scan methods are Launch-on-Capture and Launch-on-shift. In launch-on-capture, the entire test vector is loaded into the integrated circuit at the scanning frequency. Then, the integrated circuit is clocked twice by a PLL clock signal (i.e. a clock signal from a Phase Locked Loop within the integrated circuit) at the operating frequency in normal mode. The first pulse allows the entered test vector to be converted into a second test vector based on the logic functions of the integrated circuit. The second pulse generates the test results of the second test vector.
FIG. 1(a) illustrates the timing diagram of launch-on-capture scan run. For illustrative purposes, PLL clock signal PLL_CLK is only shown to have roughly three times the frequency of a scan clock signal S_CLK, which is generally provided by for test equipment coupled to the integrated circuit, however on actual test equipment and integrated circuit PLL clock signal PLL_CLK may have a frequency that is several orders of magnitude greater than the frequency of scan clock signal S_CLK. Circuit clock signal C_CLK shows the clock signal that is applied to the scan chain. Thus, in scan mode circuit clock signal C_CLK is based on scan clock signal S_CLK. However, during the actual at speed test when the second test vector and the output data is captured capture cycle clock signal C_CLK is based on PLL clock signal PLL_CLK. A scan enable signal SCAN_E determines whether the scan chain is in “scan mode” or “normal mode”. In FIG. 1(a), when scan enable signal SCAN_E is at logic high, the scan chain is in scan mode. When scan enable signal SCAN_E is at logic low the integrated circuit is in normal mode. As shown in FIG. 1(a), scan enable signal SCAN_E begins at logic high, thus at active clock edges 111 and 112 circuit clock signal C_CLK, new data is serially scanned into the scan chain. For consistency, rising clock edges are used as the active clock edge herein, however in many circuits falling clock edges are used as the active clock edges. Some circuits may even use both rising and falling edges as active edges. Active clock edge 112 clocks the last bit of the test vector into the scan chain. Thus, after active clock edge 112, scan enable signal SCAN_E transitions to logic low and the scan chain is in normal mode. After the transition of scan enable signal SCAN_E to logic low, circuit clock signal C_CLK may be held at logic low for a few clock cycles of PLL clock signal PLL_CLK. Then, at active clock edge 114, which is based on PLL clock signal PLL_CLK, the normal logic functions of the scan chain is performed to generate the second test vector. Then, at active clock edge 115, which is also based PLL clock signal PLL_CLK, the scan chain generates the test results from the second test vector. After active clock edge 115, scan enable signal SCAN_E transitions to logic high and the scan chain is in scan mode. Thus, at active clock edges 116 and 117 of circuit clock signal C_CLK, the output data is read out serially from the scan chain (while a new test vector is scanned in).
The clock cycle beginning with active edge 112 is often called the “last scan-in shift cycle” because the last data bit for the scan vector is scanned into the scan chain. The clock cycle beginning with active clock edge 114 is often called the launch cycle because it “launches the test”. The clock cycle beginning with active clock edge 115 is often called the “capture cycle” because the test results are captured in the scan chain. Depending on the specific implementation and timing, one or more dummy cycles could be inserted between the last scan-in cycle and the launch cycle. During dummy cycles circuit clock signal C_CLK is usually held at an inactive logic state. (i.e. logic low when rising edges are active edges). Furthermore, dummy cycles could also be inserted after the capture cycle and prior to reading the data from the scan chain.
In launch-on-shift scanning, the test vector except for the last bit is scanned into a scan chain of the integrated circuit at the scanning frequency. However, the last bit of the test vector is scanned at the operating frequency and the circuits of the scan chain are operated for a second active clock edge at the operating frequency to generate the test results of the test vector. FIG. 1(b) illustrates the timing for launch-on-shift scanning. As in FIG. 1(a), for illustrative purposes the, a PLL clock signal PLL_CLK is only shown to have roughly three times the frequency of a scan clock signal S_CLK. Circuit clock signal C_CLK shows the clock signal that is applied to the scan chain. Scan enable signal SCAN_E determines whether the scan chain is in “scan mode” or “normal mode”. As shown in FIG. 1(b), scan enable signal SCAN_E begins at logic high, thus at active clock edges 121, and 122 of circuit clock signal C_CLK, the new data is serially into the scan chain. Unlike in launch-on-capture scans, for launch-on-shift scanning, the last bit of the test vector is scanned at the frequency of PLL clock signal PLL_CLK. Thus, active edge 123, which is followed by active clock edge 124 of circuit clock signal C_CLK is based on PLL clock signal P_CLK. Active clock edge 123 clocks the last bit of the test vector into the scan chain. Scan enable signal SCAN_E must transition to logic low after active clock edge 123 and before active clock edge 124. At rising clock edge 124, which is based on PLL clock signal PLL_CLK, the normal logic functions of the scan chain is performed to generate the test results. After rising clock edge 124, scan enable signal SCAN_E transitions to logic high, which places the scan chain into scan mode. Thus, at active clock edges 125, 126, and 127 of circuit clock signal C_CLK, the output data is read out serially from the scan chain (while a new test vector is scanned in).
For launch-on-shift scanning, the “launch cycle” and the “last scan-in shift cycle” are the same and begin with active clock edge 123. For clarity, the term “last shift launch cycle” is used herein to refer to the cycle that shifts the last data bit into the scan chain and launches the testing of the integrated circuit. The clock cycle beginning with active clock edge 124 is often called the capture cycle. Depending on the specific implementation and timing, one or more dummy cycles could be inserted before the last shift launch cycle. During dummy cycles circuit clock signal C_CLK is usually held at an inactive logic state. (i.e. logic low when rising edges are active edges). Furthermore, dummy cycles could also be inserted after the capture cycle and prior to reading the data from the scan chain.
As processing technology improved, the number of transistors on a single integrated circuits has increased drastically. To make use of the large number of available transistors, designers now use hierarchical design methodologies. Generally, a complex design is broken down into various layers of logic blocks. The logic blocks can be designed independently and can even be shared between different designs. The logic blocks are converted into physical blocks that are positioned in a floor plan for the integrated circuit. Furthermore, the circuits of an integrated circuit are generally divided between a number of clock domains. Clock domains could be used for circuits operating at different frequencies. Other reasons to use multiple clock domains are to lessen loads on clock lines and to reduce the length of clock lines to control propagation delay. Generally, each clock domain includes a phase locked loop to generate the clock signal for the clock domain. Thus, each clock domain in general is asynchronous as compared to other clock domains. However, circuits in different clock domains do interact. Thus, when performing launch-on-shift scanning, the timing uncertainty between circuits in different clock domains makes the circuit state during the capture cycle unpredictable. Hence there is a need or a method and apparatus for forming performing launch-on-shift scanning on integrated circuits having multiple clock domains.